A Partitioned Register File Architecture and Compilation Scheme 3 COMN

In Clustered Instruction-level Parallel (ILP) processors, the function units are partitioned and resources such as register le and cache are either partitioned or replicated and then grouped together into on-chip clusters. We present a novel partitioned register le architecture for clustered ILP processors which exploits the temporal locality of references to remote registers in a cluster and combines multiple inter-cluster communication operations into a single broadcast operation using a new sendb instruction. Our scheme makes use of a small Caching Register Buuer (CRB) attached to the traditional partitioned local register le, which is used to store copies of remote registers. We present an eecient code generation algorithm to schedule sendb operations on-they. Detailed experimental results show that a windowed CRB with just 4 entries provides the same performance as that of a partitioned register le with innnite non-architected register space for keeping remote registers.